ELINTIR ML/RF MAPPER

Company

Code that turns the spectrum into data

ELINTIR works where digital signal processing meets applied engineering. We carry a solution from the mathematics and a bench mock-up through to verified operation on real hardware — and we quote only the numbers that have made that journey.

Algorithms
The mathematics of signal processing: estimation, synchronisation, classification. What decides whether a system works at all.
Embedded software
Code that lives on the board next to the radio and keeps up with real time.
Operator interfaces
What a person actually operates this through, in the field rather than the lab.

Three stages, and none is skipped

01
Mathematics
A model, and the limits of what is possible at all on this geometry and in this band.
02
Bench
Controlled conditions, a known source, a repeatable run.
03
Real hardware
The open air, real interference — and numbers that often turn out different.
Every number carries a provenance tag

Measured on hardware, calculated, or assumed are different things, and we do not mix them. When a measurement refutes one of our own earlier results we publish the new one and say the old was wrong. A project's technical risk is set not by how many optimistic numbers it holds, but by how fast it catches its own.

Kyiv Four · full time Self-funded
Technical
Founder and CTO: signal processing, architecture, protocols.
Production and finance
Scaling assembly, supply, the economics of a node.
Testing and hardware
Assembly, field trials, power, 3D-printed tooling.
Legal and IP
Intellectual property audit, legal matters, export classification.

Everything built so far has been funded out of the team's own pockets. Not someone else's money that will run out, but our own, already committed.

These are not separate products. They decide which problems we can take on at all — and how quickly.

FPGA utilisation checking
We work out what actually fits in the die and with how much headroom, before the board becomes the project's constraint.
Antenna array analysis
Array geometry and the Fresnel zone — what decides whether the problem has a solution at all.
Protocol integration
MAVLink and others, when our module has to talk to whatever it was embedded into.
AMD export permission for the RFSoC toolchain

We hold our own export permission, agreed with AMD, for the RFSoC design software: Vivado ML Edition with UltraScale+ device licences, Vitis and Vitis HLS, Vitis Model Composer for DSP chains, PetaLinux for the processing system — and, the part that matters most here, the RF Data Converter IP core with its driver: that, not the board, is what gives access to the on-die ADCs and DACs an RFSoC is chosen for in the first place.

The bottleneck is the toolchain: without legal access to it there is no development for this part at all — nothing to generate the converter configuration with, nothing to build a bitstream with. The boards themselves come from China and need no permission.

AMD Vivado Design Suite: a software box and three claims — unified tool flow, advanced compile flows, broad IP catalog.
AMD's own illustration. Vivado ML Edition is part of the toolchain we are permitted to use.
Company ELINTIR LLC
Kyiv, Ukraine

Full measurements, the protocol specification and the code provenance audit are in the data room.

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